1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of controlling the same, and more particularly, to a memory cell of a DRAM (Dynamic Random Access Memory) and a method of controlling the same.
2. Description of the Background Art
In recent years, the demand for semiconductor memory devices is rapidly increasing due to the remarkable spread of information processing apparatus such as computers. Semiconductor memory devices having functionally large scaled storage capacity and capable of high spread operation are required. Accordingly, developments in technique are carried out regarding high density integration, quick response, and high reliability of the semiconductor memory devices.
A DRAM is well known as a semiconductor memory device being capable of random input/output of storage information. A DRAM usually comprises a memory cell array including a storage region for storing a plurality of storage information, and a peripheral circuit required for input from and output to an external source. FIG. 1 is a block diagram showing the structure of a conventional DRAM. Referring to FIG. 1, a DRAM 50 comprises a memory cell array 51 for storing data signal of storage information, a row-and-column address buffer 52 for receiving external address signals to select memory cells each forming a unit storage circuit, a row decoder 53 and a column decoder 54 for specifying a memory cell by decoding the address signal, a sense refresh amplifier 55 for amplifying and reading out the signal stored in the specified memory cell, a data-in buffer 56 and a data-out buffer 57 for data input/output, and a clock generator 58 for generating a clock signal.
The memory cell array 51 occupying a large area on the semiconductor chip has a plurality of memory cells arranged in a matrix manner, each for storing unit storage information. A memory cell is generally constituted by one MOS transistor and one capacitor connected thereto. This memory cell is well known as a one-transistor one-capacitor type memory cell. Such memory cells are widely used for large capacity DRAMs because of its simple structure contributing to the improvement in higher integration density of the memory cell array.
The memory cell of a DRAM can be classified into several types depending on the structure of the capacitor. A stacked type capacitor can have an increased capacitor capacitance by increasing the opposing area between electrodes of the capacitor through extension of the major portion of the capacitor to the gate electrode and over the field isolation film. By virtue of this characteristic, a capacitor capacitance sufficient for a stacked type capacitor can be ensured even when elements are miniaturized due to larger scale integration of the semiconductor device. The extensive usage of stacked type capacitors results from such larger scale integration of the semiconductor devices.
FIG. 2 is a sectional view of a memory cell of a conventional stacked type DRAM shown in U.S. Pat. No. 4,922,312, and Japanese Patent Laying-Open No. 57-23261, for example. Referring to FIG. 2, a conventional memory cell of a DRAM comprises a semiconductor substrate 101, an isolation region (102), an insulating film (103) for an MOS transistor, a gate electrode (word line) 104 for an MOS transistor, an impurity diffusion region 105 having a conductivity type opposite of that of semiconductor substrate 101, an interlayer insulating film 106, a lower electrode 107 of a capacitor electrically connected to diffusion layer 105, a dielectric film 108 for the capacitor, an upper electrode 109 for the capacitor, an interlayer insulating film 110, and a bit line 111 constituted by a conductor electrically connected to the diffusion layer 105 opposite of capacitor electrode 107. The MOS transistor 112 is constituted by a pair of diffusion layers 105, insulating film 103, gate electrode 104 and semiconductor substrate 101. The capacitor 113 is constituted by lower electrode 107, dielectric film 108, and upper electrode 109. This device is classified into a general one-transistor one-capacitor type MOS DRAM. The operation principle thereof as a memory is disclosed in the fifth chapter of "Introduction to MOS LSI Design", by John Mavor, Mervyn Jack, Peter Denyer, Addison-Wesley Publishing Co., for example.
FIG. 3 is an equivalent circuit diagram of a memory cell of a DRAM. Referring to FIG. 3, bit line 111 is a signal input/output line, and word line 104 is a select line. Transfer gate 112 is implemented with a MOS type transistor. The capacitance of capacitor 113 for storing signal charges is C.sub.S (storage capacity). A cell plate 116 is equivalent to upper electrode 109 of capacitor 113. Gate electrode 104 of FIG. 2 is also the gate electrode of the transistor and is extended to serve as word line 104.
The operation of the DRAM as a memory will be explained hereinafter with reference to FIG. 3. Storage is carried out by binary notation in this DRAM, as in other semiconductor memories. That is, two states of "high" and "low" logic levels are implemented for a specific memory cell. Information is stored by determination of each cell being either "H" or "L". The storage of H and L in the DRAM is distinguished by the electrode potential of capacitor 115 (indicated by A in FIG. 3, wherein this point is called the storage node) connected to the transfer gate. It is customary to define the H state and the L state as in the following manner.
H state: the potential of point A is high (V.sub.H). Electrons are physically extremely scarce than under a thermal equilibrium state.
L state: the potential at point A is low (V.sub.L). The device is normally at 0 V potential.
The absolute value may take any value of V from the standpoint of the memory's operation principle as long as a constant difference is ensured between potential V.sub.H corresponding to a H logic level and potential V.sub.L corresponding to a L logic level. In practice, V.sub.H takes the power supply voltage (V.sub.CC) of the circuit system controlling the memory cells, and V.sub.L takes the ground voltage (V.sub.SS =0 V) of the same circuit system.
The storage charge amount Q.sub.H at the H level is expressed by the following equation (1): EQU Q.sub.H =C.sub.S .multidot.V.sub.H . . .( 1)
The stored charge amount Q.sub.L at the L level is expressed by the following equation (2): EQU Q.sub.L =C.sub.S .multidot.V.sub.L . . .( 2)
The H level and the L level are distinguished by converting the difference of the storage charge amounts Q =Q.sub.H -Q.sub.L to a potential difference and reading it out. A differential amplifier circuit of high sensitivity called a sense amplifier is used for this purpose. The operation thereof is conventionally known, and its description is found in the aforementioned "Introduction to MOS LSI Design".
It is to be noted that potential V.sub.GG of cell plate 116 of FIG. 3 does not affect the differential charge stored. This means that V.sub.GG may take any value of V as long as it is a constant potential to operate the DRAM.
Accordingly, the power supply voltage V.sub.CC of the circuit or the ground voltage V.sub.SS was used as V.sub.GG in DRAMs of mass production. The area occupied by capacitors in such DRAMs are reduced to increase integration density of DRAMs. On the other hand, the reduction of capacitor capacitance C.sub.S is limited due to the fact that S/N (signal-to-noise ratio) of the circuit must be ensured to prevent malfunction (at least 20 fF is necessary under the present condition). This results in the necessity of reducing the thickness of the dielectric film of the capacitor to increase the capacitance per unit area. That is to say, capacitance C.sub.S of the capacitor is expressed by the following equation (3). ##EQU1## S: Opposing area of capacitor d: dielectric film thickness
.epsilon..sub.0 : vacuum permittivity PA1 .epsilon.: relative permittivity PA1 .epsilon..sub.0 .multidot..epsilon.: permittivity of dielectric film PA1 E : applied field strength PA1 .alpha.: field acceleration factor
The idea is to compensate for reduction in opposing area S of the capacitor in equation (3) with decrease of the dielectric film thickness d. However, there was an inconvenience from the standpoint of reliability of the dielectric film due to the increase of electric field strength E exerted on the dielectric film. It is generally known that the mean time to failure (referred to as MTTF hereinafter) of the dielectric film has high correlation with the applied electric field E, as in the following equation (4). EQU MTTF.degree. C.e.sup.-.alpha..multidot.E ( 4)
Approximately 1.5/(MV/cm) was measured for the value of .alpha. using SiO.sub.2 as the dielectric film. This means that the lifetime of the film (assumed to be 10.sup.n seconds) is reduced by n=1.5 as a function of electric field applied to SiO.sub.2 increasing 1 MV/cm.
A method to solve the short lifetime of the film is proposed in Japanese Patent Publication No. 60-50065, for example. The approach is to reduce cell plate potential V.sub.GG to one half of the logic voltage swing of the memory, which is equivalent to power supply V.sub.CC of the circuit in most cases.
FIG. 4 is a sectional view of a planar type DRAM cell proposed in Japanese Patent Publication No. 60-50065. Referring to FIG. 4, the capacitor is implemented with a diffusion layer 205 at the surface of a silicon substrate 201 as one electrode and a cell plate 209 as the other electrode. The interlayer insulating film 217 of the capacitor is formed of SiO.sub.2 produced by thermal oxidation of silicon substrate 201. The feature of the invention disclosed in Japanese Patent Publication No. 60-50065 is to reduce the potential of cell plate 209 to one half of the logic voltage swing written in the memory (it is assumed to be V.sub.CC here). The obtained advantage is obvious from the values of electric field E applied to the SiO.sub.2 film shown in the following Table 1.
TABLE 1 ______________________________________ E (High) E (Low) Q ______________________________________ V.sub.CC Cell Plate +V.sub.CC /d 0 C.sub.S .times. V.sub.CC V.sub.SS Cell Plate 0 -V.sub.CC /d C.sub.S .times. V.sub.CC 1/2 V.sub.CC Cell Plate +V.sub.CC /2d -V.sub.CC /2d C.sub.S .times. V.sub.CC ______________________________________
The directions of the electric field (code) are different in the conventionally employed V.sub.CC cell plate (V.sub.GG =V.sub.CC) method and V.sub.SS cell plate (V.sub.GG =V.sub.SS) method. The absolute value of the electric field strength applied to the insulating film is V.sub.CC /d. By setting the cell plate potential to 1/2 of V.sub.CC, the absolute value of electric field strength is V.sub.CC /2d in either case of H storage and L storage, which is one half of that in comparison with V.sub.CC and V.sub.SS cell plates.
However, the electric field applied time of 1/2 V.sub.CC cell plate is averagely two times of that of V.sub.CC and V.sub.SS cell plates, assuming that the probability of H being stored and L being stored the same.
The electric field strength reliance of the insulating film's lifetime is great as mentioned before. For example, n=1.5 MV/cm in the case of SiO.sub.2. It is advantageous from the standpoint of reliability to reduce the electric field to one half even if the time is doubled. It should be noted that the purpose of employing a 1/2 V.sub.CC cell plate is to equal the absolute values of the electric field applied to the capacitor dielectric film, such as +V.sub.CC /2d at the time of E (High) and -V.sub.CC /2d at the time of E (Low). (Although there may be slight deviation due to fluctuation of the cell plate potential generating circuit, the target is 1/2 V.sub.CC.) This is based on the fact that the lifetime of the insulating film is the same regardless of whether the electric field of the capacitor is positive (cell plate side is high potential) or negative (storage node, the A side in FIG. 3 is high potential).
FIG. 4 shows a structure of a cell around the time when Japanese Patent Publication No. 60-50065 was filed. That is to say, a silicon substrate is one electrode of the capacitor, whereby the surface thereof is thermally oxidized to a SiO.sub.2 capacitor insulating film. The lifetime of the insulating film depends only on the magnitude of the absolute value of the electric field regardless of the direction of the electric field. It has been confirmed by experiment that the field acceleration factor o is approximately 1.5/ (MV/cm).
The area occupied by one cell is further reduced according to the DRAM scaled to higher densities. The area that can be used for capacitors is reduced significantly in cells having structures shown in FIG. 4. Therefore, a cell structure of a stacked type shown in FIG. 2 has been employed for the structure of capacitors. Such capacitors are implemented with two conductive thin films as an upper electrode 109 and a lower electrode 107, with a dielectric film 108 therebetween. Lower electrode 107 corresponds to the storage node of A of FIG. 3. The storage node is patterned as separate cells with the lower portion thereof electrically connected to diffusion layer 105, where signal charge is input/output.
The upper electrode 109 is electrically, and in most cases physically, connected to a plurality of cells as a cell plate, wherein the entire cell plate is held at a constant cell plate potential V.sub.GG.
It is shown in FIG. 2 that storage node electrode 107 extends above transfer gate electrode 104 and isolation region 102 to expand the effective area as a capacitor. Upper and lower electrodes 109 and 107 are formed of polysilicon film or the like where resistance value is reduced by being contaminated with impurities such as phosphorus and arsenic. Such polysilicon films are normally formed by low pressure CVD method, in which impurities are introduced at the time of or after CVD film formation.
When the lower electrode is of polysilicon and a capacitor insulating film 108 is to be formed thereabove, the thermal oxidation method described in association with FIG. 4 may of course be adopted. It has become obvious from experiments that reliability of the generated SiO.sub.2 is extremely inferior because the polysilicon film is oxidized. The cause may be due to the generation of weak spots of low reliability scattered in the thermal oxidized film resulting from significant polycrystal grain boundary migration of the underlying polysilicon during oxidization. Therefore, insulating films formed by CVD method are mainly used for stacked type capacitor structures as of FIG. 2.
Any material may be selected for the formation of the film, regardless of the underlying material if the capacitor insulating film is formed by the CVD method. A silicon nitride film (Si.sub.3 N.sub.4) is often used because the permittivity thereof is about two times of that of SiO.sub.2, whereby the capacitor capacitance C.sub.S indicated in the aforementioned equation (3) can be ensured. However, leak current through the entire film is great when a Si.sub.3 N.sub.4 film formed by CVD method is used solely as a capacitor dielectric film. Therefore, Si.sub.3 N.sub.4 film formation is generally followed by oxidation of the surface thereof under oxidizing high temperature atmosphere to form a structure of an ON (Oxidized Nitride) film.
FIG. 5 is a sectional structure view for explaining in detail the capacitor dielectric film of the stacked type DRAM cell of FIG. 2. Referring to FIG. 5, a capacitor dielectric film 108 comprises a Si.sub.3 N.sub.4 film 108a deposited by CVD, and a SiO.sub.2 film 108b formed by oxidizing Si.sub.3 N.sub.4 film 108a. There is a very thin SiO.sub.2 layer (not shown) at the boundary of underlying polysilicon (lower electrode 107) and CVD deposited Si.sub.3 N.sub.4 film 108a. This thin layer is formed due to the polysilicon surface being slightly thermal oxidized before the film is deposited in forming Si.sub.3 N.sub.4 film 108a by CVD method over the polysilicon (lower electrode 107) at a temperature of not less than approximately 700.degree. C. The thickness of the SiO.sub.2 layer is estimated to be not more than approximately 0.5 nm in a low pressure CVD device.
The cell plate potential has also employed the 1/2 V.sub.CC in the stacked type DRAM cells of FIGS. 2 and 5. This is because the feature of the reliability of the SiO.sub.2 type ON film was not clearly comprehended. The customarily employment of 1/2 V.sub.CC is only the result of conventional selection.
The above mentioned ON film is applicable to not only a stacked type capacitor such as of FIG. 2, but also to a trench type capacitor having a capacitor electrode formed in an excavated groove in a substrate. Most existing DRAMs with trench type capacitors employ a similar ON film and the 1/2 V.sub.CC cell plate method.
In conventional MOS type DRAMs, the cell plate voltage was set to 1/2 V.sub.CC to minimize the electric field within the dielectric film when thermal oxidized SiO.sub.2 films are used as dielectrics, as mentioned before. Then, a cell structure of the stacked type or the trench type was employed for the purpose of expanding the effective area of the capacitor. In order to avoid the influence of polycrystal grain boundary migration in such cases, an ON film was used as a dielectric film formed mainly of Si.sub.3 N.sub.4 deposited by CVD.
The aforementioned selection of 1/2 V.sub.CC for V.sub.GG had the following grounds. That is, the reliability of the dielectric film is irrespective of the direction of the electric field applied to the capacitor electrode, as in the case where a silicon thermal oxide film is formed over a monocrystal silicon. There was also the physical fact that the effect of electric field reduction is more advantageous than the effect of the field application time upon the lifetime from the standpoint of reliability.
The ON film used in capacitors of the stacked type or the trench type with a two layer structure (a three layer structure to be exact) of oxide film/nitride film is asymmetric in the direction of film thickness. Therefore, there is possibility that the above mentioned conditions do not apply. Nevertheless, a 1/2 V.sub.CC cell plate was employed in DRAMs of the conventional stacked type or trench type capacitors. Accordingly, there was a disadvantage that degradation is seen at a time period significantly shorter than the normal lifetime of the capacitor dielectric film.